RAM and ROM in barretenberg

ROM Table

  • ROM: fixed read only table
index name base location
0 suyash mumbai
1 raju berlin
2 federico london
3 ariel krakow
  • Can I prove in a SNARK circuit that I read a ROM entry (and use it)?

ROM Table in Circuit

index name base location
0 suyash mumbai
1 raju berlin
2 federico london
3 ariel krakow
a b c d
2 fede london
\vdots
\vdots
r_i
r_i = \textcolor{red}{\eta_1} \cdot 2 + \textcolor{red}{\eta_2} \cdot \texttt{fede} + \textcolor{red}{\eta_3} \cdot \texttt{london}
  • ROM gate \(\longleftrightarrow\) row in ROM table
  • 4th wire contains record:
  • Sorted ROM gates: check if indices increase monotonically
  • If index is same for two adjacent gates, values must be same!
\textsf{gate }i

RAM Table

  • RAM: updatable memory
index name base location
0 suyash mumbai
1 raju berlin
2 federico london
3 ariel krakow
  • Can I prove in a SNARK circuit that I read/wrote a RAM entry (and used it)?
\texttt{amsterdam}

4

\texttt{jony}
\texttt{sydney}

RAM Table in Circuit

index name base location
0 suyash mumbai
1 raju berlin
2 federico london
3 ariel krakow
\texttt{amsterdam}

4

\texttt{jony}
\texttt{sydney}
a b c d
2 london
\vdots
\vdots
t_i
r_i
\textsf{gate }i
  • RAM: 1-d memory (think: cpp array)
  • RAM gate needs a timestamp \(t_i\)
  • RAM record:
r_i = \mathbb{I}_{\textsf{W}} + \textcolor{red}{\eta_1} \cdot 2 + \textcolor{red}{\eta_2} \cdot \texttt{fede} + \textcolor{red}{\eta_3} \cdot \texttt{london}
  • Ensure timestamps are correct
  • Ensure read/writes are correct

ROM and RAM in barretenberg

By Suyash Bagad

ROM and RAM in barretenberg

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